Volume 17-Issue4-2008-LE BEUX

A Model Driven Co-Design Approach for High Performance Embedded Systems Dedicated to Transport

Sébastien LE BEUX, Philippe MARQUET, Jean-Luc DEKEYSER
LIFL, INRIA Lille-Nord Europe and University of Lille, France

Abstract: This paper demonstrates that the Model Driven Engineering approach is reliable for the development of codesign environments dedicated to embedded systems. From a UML model of a data parallel application, the Gaspard environment is able to generate an hardware accelerator which executes the modeled application. All the potential parallelism of a given application is modeled in UML and is exploited in order to generate a powerful hardware system. Gaspard is dedicated to intensive signal processing applications. Therefore, many automotive sector applications could benefit of the Gaspard environment.

Keywords: Model Driven Engineering, embedded systems, data parallelism, FPGA, intensive signal processing.

Sébastien Le Beux is currently post-doctoral researcher at the École Polytechnique of Montreal, Canada. He received a PhD. in computer science from the University of Lille in 2007. His research interests include the design of parallel, embedded and reconfigurable architectures, model driven engineering and the mapping of intensive signal processing applications onto network on chip.

Philippe Marquet is currently an assistant professor at the University of Lille, France and a researcher within the INRIA, the French institute for research in computer science. Philippe MARQUET received a Ph.D. in Computer Science from the University of Lille in 1992. His research interests include the design of parallel, embedded and reconfigurable architectures, the definition of programming models, languages and compilers dedicated to parallel computing. He also worked on the definition and implementation of real-time operating systems for SMP architectures. He (co-)advised 10 Ph.D thesis.

Jean-Luc Dekeyser received his PhD degree in computer science from the University of Lille in 1986, he was a fellowship at CERN Geneva. After a few years at the Supercomputing Computation Research Institute in Florida State University, where he worked on high performance computing for Monté-Carlo methods in High Energy Physics, he joined in 1988 the University of Lille in France as an assistant professor. There he worked on data parallel paradigm and vector processing. He created a research group working on High Performance Computing in the CNRS lab in Lille. He is currently Professor in computer science at University of Lille. He is heading the DaRT INRIA project. His research interests include embedded systems, System on Chip co-design, high performance computing, model driven engineering.

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CITE THIS PAPER AS:
Sébastien LE BEUX, Philippe MARQUET, Jean-Luc DEKEYSER, A Model Driven Co-Design Approach for High Performance Embedded Systems Dedicated to Transport, Studies in Informatics and Control, ISSN 1220-1766, vol. 17 (4), pp. 407-420, 2008.

1. Introduction

Complexity of the automotive embedded applications continuously increases. Anti-collision radar, vehicle tracking and inter-vehicle communication are some examples of such applications which have to be embedded in a system.

Most of the time, embedded systems have real-time constraints and have to satisfy various constraints, such as energy consumption, surface, etc. The “System on Chip” (SoC) allow to design mix hardware and software embedded systems. SoC are realized on a single chip, therefore, they help to solve embedded systems constraints. The current SoC generation already contains several processors on a single chip: a general purpose processor (ARM, etc.), DSP dedicated to digital signal processing applications, ASIC for very specific and systematic tasks and reconfigurable components, FPGA, which add flexibility to a SoC. The rising integration capabilities of the chips allows to design more “parallel” SoC, where several homogeneous or heterogeneous processors communicate according to bus or complex Network on Chip (NoC). The next SoC generation has to provide more and more computing power and still has to satisfy the energy consumption constraints.

The rising complexity of the automotive application and the rising SoC integration capabilities are the trend. However, it is an ambitious challenge to efficiently execute such complex applications onto such complex architectures. In order to successfully face this challenge, it becomes necessary to relevantly exploit the specificity of hardware and software elements contained in embedded systems. A hardware element corresponds to an architectural component in a SoC (i.e. processors, memories, etc.), a software elements corresponds to a task in an application. Some approach aim to specify the software independently from the hardware in order to facilitate the design of embedded system. The software and the hardware are tested together only at the end of the design process, they can reveal some major problem that could have been detected earlier with a co-design approach.

The co-design approach aims to specify, at the same time and in the same environment, the hardware and the software embedded in a system. For this purpose, it is necessary to model both the hardware and the software in the unified environment in order to accelerate the design process and to increase the productivity of the SoC designers.

This paper extends the works presented in [6] and demonstrates the reliability of the Gaspard codesign environment to develop high performance systems. Gaspard is introduced in Section 2; this environment is definitely oriented towards regular parallel applications and architectures. Section 3 presents the high level modeling of a purely data parallel application used in an embedded automotive radar. From this high level model, the VHDL code is automatically produced and synthesized onto FPGA. On-road experimentation results of the overall embedded system are provided in Section 4, demonstrating the reliability of our approach. The conclusion presents the extension of our work for control-flow and mix data-flow/control-flow applications.

5. Conclusion

This paper presents the Gaspard co-design environment, which is dedicated to the embedded systems. From a UML model of an application, Gaspard generates the VHDL code corresponding to a hardware accelerator able to execute the modeled application. The VHDL code can be synthesized and implemented onto FPGA according to synthesis tools. The UML models are independent from any implementation details. Therefore, one can model an application and generate the corresponding hardware accelerator without being expert in the design of hardware accelerators.

We demonstrate the reliability of the Gaspard environment for data parallel automotive applications. For this purpose, a detection algorithm embedded in anti-collision radar was modeled in UML. The hardware accelerator generated by Gaspard was synthesized onto FPGA. After simulation processes and validations, the hardware accelerator was experimented on-road. This experimentation validated the right behavior of the hardware accelerator and the overall embedded system.

6. Acknowledgements

We acknowledge the LT’2007 staff for their recommendation in the submission of this extended variant of our works.

REFERENCES

ATITALLAH, R. B., S. NIAR, J.-L. DEKEYSER, MPSoC Power Estimation Framework at Transaction LevelModeling. In The 19th International Conference on Microelectronics (ICM 2007), Cairo, Egypt, Dec. 2007.
ATITALLAH, R. B., E. PIEL, S. NIAR, P. MARQUET, J.-L. DEKEYSER, Multilevel MPSoC simulation using an MDE approach. In: IEEE International SoC Conference (SoCC 2007), Hsinchu, Taiwan, Sept. 2007.
BOULET, P., Array-OL revisited, multidimensional intensive signal processing specification, Research Report RR-6113, INRIA, Feb. 2007.
CUCCURU, A., J.-L. DEKEYSER, P. MARQUET, P. BOULET, Towards UML 2 extensions for compact modeling of regular complex topologies. In: MoDELS/UML 2005, ACM/IEEE 8th International Conference on Model Driven Engineering Languages and Systems, Montego Bay, Jamaica, Oct. 2005.
CZARNECKI, K., S. HELSEN, Classification of model tranformation approaches. In: Proceeding of OOPSLA Workshop on Generative Techniques in the Context of Model Driven Architecture, 2003.
DEKEYSER, J.-L., S. LE BEUX, P. MARQUET, Une approche mod`ele pour la conception conjointe de systmes embarques hautes performances ddis au transport. In: Workshop International: Logistique & Transport (LT’2007), Sousse, Tunisie, Nov. 2007.
eclipse.org. Eclipse. http://www.eclipse.org, 2005.
HILLALI, Y. E., A. RIVENQ, O. LABBANI, J. ROUVAEN, Study of a Intelligent Cruise Controlwith GPS and Radar. In: International ModEasy’07 Workshop, Barcelona, Spain, Sept. 2007. http://www2.lifl.fr/modeasy/workshop.html.
GAJSKI, D. D., R. KUHN, Guest editor introduction: New VLSI-tools, IEEE Computer, 16(12):11-14, Dec.1983.
HILLALI, Y. E., Etude et ralisation d’un systme de communication et de localisation, bas sur les techniques d’talement de spectre aux transports guids, PhD thesis, University of Valenciennes, 2005. (In French).
LABBANI, O., E. RUTTEN, J.-L. DEKEYSER, Safe design methodology for an intelligent cruise control system with GPS. In: 64th IEEE Vehicular Technology Conference (VTC 2006), Montral, Qubec, Canada, Sept. 2006.
LE BEUX, S., Un flot de conception pour applications de traitement du signal systmatique implmentes sur FPGA base d’Ingnierie Dirige par les Modles, Thse de doctorat (PhD Thesis), Laboratoire d’informatique fondamentale de Lille, Universit des sciences et technologies de Lille, France, Dec. 2007.
LE BEUX, S., P. MARQUET, O. LABBANI, J.-L. DEKEYSER, FPGA implementation of embedded cruise control and anti-collision radar. In: DSD’2006, 9th Euromicro conference on digital system design, Dubrovnik, Croatia, Aug. 2006.
SEIDEWITZ, E., What models mean, IEEE Softw., 20(5):26-32, 2003.
TESSIER, R., W. BURLESON, Reconfigurable computing for digital signal processing: A survey, The Journal of VLSI Signal Processing, 28(1-2):7-27, Dec. 1999.