This paper describes all steps for high speed complex multiplying chip design. The architectures developed and tested for this chip will be used to build an FFT processor. The described architecture allows very high processing speed. In DSP processor manner, the chip processing speed is approx. 40-50 MIPS. The used algorithm, CORDIC, is presented in Section 2 of the paper. This algorithm can evaluate the results of parallel multiplying by trigonometrical functions without explicitly computing these functions or without explicitly computing the product. The algorithm can be used for many other types of mathematical functions, but this paper personalizes it for complex rotation. Section 3 of the paper addresses number representation and certain problems of the integer number arithmetic. The whole project was carried out using a behavioural description in VHDL language. Section 4 includes the presentation of the architecture. Experimental results are presented in the last Section of the paper.
DSP, CORDIC, VLSI, FPGA, hardware, integer number arithmetic.
All articles published by Studies in Informatics and Control (SIC) are published in accordance with the terms and conditions of the Creative Commons Attribution License (CC BY-NC-SA 4.0).